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Advanced packaging challenges are getting more and more severe

Using existing inspection tools to find defects becomes more difficult, but the cost of upgrading to new technologies is high.

The defect detection systems currently used for packaging have been unable to cope with the latest advanced packaging, which has prompted the market to demand new tools.

In response, some vendors are introducing new defect detection systems for a variety of advanced packaging, such as 2.5D / 3D technology and fan-out technology. The new defect detection system is more powerful than previous tools, but it is also more expensive. Packaging plants may need to purchase different types of tools.

All of this happens when the industry tries to reduce the overall cost of advanced packaging. For many years, the industry has been using a variety of inspection equipment to locate defects in IC packages. The existing defect detection system is suitable for commercial packaging, and is also applicable to advanced packaging types currently on the market, such as 2.5D / 3D technology, fan-out technology, and the like.

But the latest advanced packaging is moving to more granular features, with more layers and more I/O. As a result, defects become smaller and smaller, and it is difficult to find defects using current inspection systems. Failure to detect defects directly affects the yield of the device.

Stephen Hiebert, director of advanced marketing at KLA-Tencor, said: "In many cases, core detection technologies for large sizes, such as the first generation of embedded wafer-level ball grid arrays (eWLB), are now ineffective, and new detection technologies are Deployment. You used to have macro inspection (for IC packaging). Now these tools for advanced packaging must be able to detect micron and submicron defects."

For example, the embedded wafer level ball grid array (eWLB) is one of a variety of fan-out packages on the market. Typically, fan-out is measured by the line and space features in the redistribution layer (RDL) within the package. The RDL consists of copper metal wires arranged in the package. Line and space refer to the width of the metal traces and the space between them.


Figure 1: Redistribution Layer (RDL) is used to rearrange the connection to the desired location. (Source: Lam Research)

As more complex chips are integrated into the fan-out package, more RDL layers with finer wiring and space may become necessary. For example, today's fan-out packages range from 5μm and above to 5mm and beyond (5-5μm) to 2-2μm and below.

Jan Vardaman, president of TechSearch International, said: "As the company moves to the next technology node, the bump pitch becomes finer and the detection capability must increase. As features (wiring and space) shrink to 2μm and below, it is found Defects become more difficult. In addition, in some applications, it has been found that debris in the vias becomes a problem."

All in all, the industry needs new defect detection systems to handle the latest advanced packaging. These features are critical in a variety of applications, such as automotive, because they require zero defects. These capabilities are also needed in other markets.

To address these challenges, KLA-Tencor, Rudolph and others have recently introduced new optical defect inspection equipment for advanced packaging that can handle RDLs up to 5μm. In addition, the supplier has introduced new infrared inspection tools for the die sorting production phase.

Packaging trend

Over the years, the focus of the IC market has been around traditional chip miniaturization, adding more functionality to the device and then shrinking the device at each process node. The package was thought of after the fact, just to install the device.

Recently, however, the miniaturization of the chip at each node has become more expensive and complicated. Today, only a few people can afford to design chips on advanced nodes. For example, according to IBS data, only IC design costs jumped from $51.3 million in 28nm planar devices to $197.8 million in 7nm chips.

This does not mean that the chip manufacturer has stopped shrinking. But analog, RF, and other chip technologies don't require advanced nodes, and these technologies are rapidly evolving. "We do expect that cars and technologies such as power management, RF and embedded non-volatile memory will grow steadily," said Steven Liu, senior vice president of marketing at Lianhua Electronics.

Advanced packaging is part of it. Since the turn of the century, the industry has been looking for alternatives to chip miniaturization, which is advanced packaging. The idea behind advanced packaging is to integrate the die vertically, rather than miniature features on a single die.

Advanced packaging has been used in niche applications for a limited number of decades. The problem is cost, because this technology is still too expensive for many applications.

As the industry moves toward the concept of so-called heterogeneous integration, advanced packaging continues to make progress. David McCann, vice president of package development and operations at GlobalFoundries, said: "The key area we need to contribute to packaging and testing is heterogeneous integration. This allows for the packaging of multiple chips, whether one node or multiple nodes. You can even import multiple vendors into the integrated package level."

To give an example of this trend, the industry has introduced 2.5D technology. In 2.5D, the die is stacked on top of an interposer containing through-silicon vias (TSVs), which act as a bridge between the chip and the board, providing more I/O and bandwidth.170439.jpg

Figure 2: FPGA + HBM in a 2.5D package with an interposer. (Source: Xilinx)

McCandan said: "2.5D increases the interconnect density by an order of magnitude. What you have to solve is memory bandwidth and latency. This is the purpose of having a very fine layer of interleaving and space."

For example, GlobalFoundries has introduced 2.5D / 3D technology with a TSV of 5μm (diameter) × 55μm (depth). The TSV of the standard is 2 μm x 20 μm.

Other packages are moving closer to finer features, fan-out. In fan-out, the die is packaged on the wafer.


The fan-out introduced more than a decade ago has a large RDL size and few I/O. In contrast, today's high-density fan-out has more than 500 I/Os and less than 8μm of wire/space. TSMC's InFO technology is the most famous fan-out technology used in the latest iPhones.

KLA-Tencor's Hiebert said: "Today, we have seen an order of magnitude reduction. We have seen 2μm of RDL for production, and 1μm and below of RDL is under development."

Some fan-out packages have three to four layers of RDL. Hiebert said: "The industry is trying to move to more RDL layers, finer-pitch RDL layers, and larger packages. If you have fan-out or multi-die fan-out, the space will be larger. The expansion of packaging, the increase in the number of layers and the reduction in RDL all pose huge yield challenges. It is critical to detect and control defects."

This is where the defect detection applies. Eelco Bergman, director of sales and business development at ASE, said: "As the connection and space become thinner, the challenge becomes more and more difficult."

Bergman said: "As you move to finer RDL, especially multi-layer RDL, how do you detect quality? You need some mechanism to monitor inline performance to drive process optimization and maximize yield. For others In the case, you may need at least some post-fabrication verification capabilities."

This is just a challenge for fan-out technology. There are other challenges in the 2.5D/3D package. There are other types of packages under development, such as chiplets, which may lead to new packaging methods.

The chiplet is more like a LEGO-block type method that uses interconnect structures to connect various pre-developed hard IP blocks. DARPA is taking the lead in this direction to reduce costs and time to market, and many companies are exploring similar options, including Intel, eSilicon and Qualcomm.

Amin Shokrollahi, CEO of Kandou Bus, said: "Our goal is to put all the features of the chip on smaller dies and increase flexibility. You can assign different parts of the neural network to the chiplet, but for flexibility, The layout of the die is very important and the space must be very short."

The final look of these chiplet packages is unclear, and the challenges of detection are unclear. Nonetheless, the overall trend, like other types of packages, is to reduce the distance and overall area to improve performance and reduce power and area.

The role of detection

To detect defects, the packaging company uses defect detection, metrology tools, and fault analysis systems. Testing is the art of discovering product defects that are used in both fab and packaging plants. This cannot be confused with metering, which refers to the measurement and characterization of the structure of the device.

Fabs and packaging plants use different inspection systems, although both are struggling to achieve similar goals—they want to find and eliminate fatal flaws in the device to increase yield.

In fabs, chips are measured in nanometer scale and defects are sometimes in the ohms class. To this end, chip manufacturers have to use expensive electron beam and optical wafer inspection systems.

In packages, the defect size is larger and is measured at the micron or submicron level. Packaging plants use tools based on optical, infrared and other technologies.

Typically, fabs and packaging plants have different inspection requirements. Tim Kryman, senior director of corporate marketing at Rudolph Technologies, said: "Although the development of advanced packaging processes may be just a migration of front-end technology to back-end operations, the structures and materials used in the packaging process are usually not present at the front end. Therefore, they With unique inspection and measurement requirements, existing front-end tools cannot meet these requirements."

For the most part, detection is relatively inexpensive for packaging, but is changing at some point. Kryman said: "The challenge for these suppliers is the changing economic model. Traditionally, packaging is considered low-tech and low-cost. Low prices and low profit margins put pressure on companies to force them to operate. Cost and capital costs are kept to a minimum. Advanced packaging processes now require investment in equipment and technology traditionally found in front-end plants."

Found defect

In traditional inline packaging processes, packaging plants use optical-based high-speed defect detection systems. Camtek, KLA-Tencor, Rudolph and other companies sell systems in this market.

Older inspection tools are available for most package types and will continue to be used for many years, but for the latest 2.5D/3D and fan-out technologies, the situation is different.

Typically, inspection tools can find defects that are one-third to one-half the size of a critical dimension. For example, for some time, the packaging factory is developing a 10μm RDL package. To do this, they use a detection system that detects defects of 3 μm and above.

But this is not good enough for the latest packages, which have RDLs of 5μm and below. Therefore, suppliers need inspection tools that can detect defects of 2.5μm and below, even sub-micron.

According to Hiebert of KLA-Tencor, “These processes are becoming more and more complex. Therefore, there is more inline monitoring using detection and measurement data. And you use it to increase the yield from research and development to high-volume production. Many detection technologies that can operate at 10μm or 20μm RDL do face challenges of reaching 1μm or lower."

This includes the latest fan-out package. In the fan-out packaging process, the chip is first processed on the wafer of the fab. The chip is then diced and placed on a wafer-like epoxy-based molding compound.

Then create a multi-layer RDL stack on top. To make the RDL, a layer of copper seed is deposited on the surface. The desired RDL structure is then patterned and developed.

At this point, the structure needs to perform a defect detection step. If there is a defect, the packaging company can solve the problem by reprocessing the wafer.

However, even with all these steps, it is still difficult to find all the defects. Amandine Pizzagalli, an analyst at Yole Development, said: "There are many flaws in advanced packaging applications."

According to Seung Wook Yoon, Director of Technology Strategy at JETET Group, there are at least three major defect challenges in current advanced packaging. “First, tiny or thin foreign objects/residues may be present at the bottom of small vias in the dielectric layer. Second, when the space is narrow and the metal lines are high (large aspect ratio), the metal lines and spaces (ditch) There is a thin metal bridge at the groove structure. Third, multi-layer RDL inspection is challenging to detect foreign matter in finer line widths and line spacings."

This, in turn, drives the need for better detection. Rudolph's Kryman said: "As with the front end, the shrinking feature size is driving inspection requirements to improve accuracy, sensitivity and throughput. The RDL line geometry is already less than 10μm and the defect sensitivity is about print line and space size. The 50% case continues to shrink. Bump size, pitch and height continue to decline. Manufacturers also face the challenge of packaging process diversity and rapid changes in demand."

Some of these requirements are the result of the package itself, which is the driving force behind the various new methods being developed to limit problems such as warpage, which itself can lead to defects. In fact, a few steps before the actual packaging will solve this problem.

Rama Puligadda, executive director of advanced technology research at Brewer Science, said: "One option is to use a thin film pre-bond to place the chip in a template of a mold compound. The result is no warpage. EMC (epoxy molding compound) is a growing problem. You can also take a more modular approach to reduce warpage."

In any case, detection requires identification of new and complex patterns. “The metal patterns of applications like fan-out are often very complex. We see more irregular shapes than front-end applications. We see diagonals. We see other structures that are not electrically intrinsic. See the structure inserted into the metal layer for thermal or structural reasons."

At the same time, in response to these and other challenges, companies such as KLA-Tencor and Rudolph have introduced new optical defect inspection tools for RDLs of 5μm and above.

The supplier's latest system uses brightfield and darkfield technologies. In brightfield imaging, the spot is directly above the sample. Light is applied to the sample and the system collects scattered light from the object. In dark field imaging, light is incident on the sample from an angle. In both cases, the data was analyzed for defects.

Each vendor also offers different features on its system. KLA-Tencor's new Kronos 1080 system is designed to detect advanced wafer-level packaging process steps. It provides flexible substrate handling to support bonded, thinned, warped and cut substrates. The tool uses a technology called FlexPoint that concentrates the system on critical areas of the die. This is where the defect has the greatest impact.

At the same time, like the previous version, Rudolph's new Dragonfly G2 platform combines 2D and 3D inspection and metering capabilities into one platform. But it has higher throughput and sensitivity. It can detect defects as small as 1μm. In addition, it adds a technology to detect non-visual defects.

More testing

After this process, the package moves to the final test and assembly, sometimes referred to as die electrical sorting. This process cuts and inspects the package.

There may be several issues here. The low-k materials used in today's devices are fragile. At the cutting or other step, cracks may appear on the side of the fan-out package, as well as on the memory package and die.

Pieter Vandewalle, general manager of ICOS at KLA-Tencor, said: “These materials are more susceptible to breakage and breakage during the cutting process. Some new defects have emerged, such as these cutting cracks, which require new testing methods.”

For this application, KLA-Tencor has entered the market for chip power characterization through an infrared-based system. KLA-Tencor's new ICOS F160 system for inspection and mold sorting. The tool also supports six-sided optical inspection.

At the same time, Mühlbauer and other suppliers are also competing in the field of chip electrical feature selection.

The way forward

As the industry is accelerating the next generation of packaging, new inspection tools will follow. These systems hope to solve the yield/defect problem.

However, the industry must address cost issues. In general, advanced packaging is still too expensive for many OEMs. Apple and some other companies are exceptions.

This must be changed. Traditional chip miniaturization has become very expensive, and many OEMs are looking at advanced packaging more rigorously. The question is whether the packaging company can cope with the cost and yield challenges of the next wave of technology.