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2018

10/26

PCB schematic wiring common error summary

1. Schematic common mistakes:

(1) The ERC report pin has no access signal:

a. I/O attributes are defined for the pins when the package is created;

b. The inconsistent grid attribute is modified when the component is created or placed, and the pin is not connected to the line;

c. When creating a component, the pi n direction is reversed and must be connected to a non-pin name.

(2) The component runs outside the drawing boundary: no component is created in the center of the chart library of the component library.

(3) The created project file network table can only be partially transferred to pcb: when the netlist is generated, it is not selected as global.

(4) Never use annotate te when using a multi-part component created by yourself.


2. Common errors in PCB:

(1) The report NODE was not found when the network was loaded:

a. The components in the schematic use packages that are not in the pcb library;

b. The components in the schematic use packages with inconsistent names in the pcb library;

c. The components in the schematic use the inconsistent package of the pin number in the pcb library. For example, the triode: the pin number in sch is e, b, c, and the pcb is 1, 2, 3.

(2) It is always impossible to print to one page when printing:

a. The pcb library is not created at the origin;

b. Move and rotate the component multiple times, there are hidden characters outside the pcb board. Select to display all hidden characters, reduce the pcb, and then move the characters to the boundary.

(3) The DRC reporting network is divided into several parts:

Indicates that this network is not connected, look at the report file, use the option CONNECTED COPPER to find.

Also remind friends to use WIN2000 as much as possible to reduce the chance of blue screen; export files several times to make new DDB files.

Reduce file size and chances of PROTEL zombie. If you are designing more complicated, try not to use automatic routing.

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In the PCB design, wiring is an important step to complete the product design. It can be said that the previous preparation work is done for it. In the whole PCB, the wiring design process is the highest, the trick is the finest, and the workload is the largest. PCB The wiring has single-sided wiring, double-sided wiring, and multilayer wiring.

There are also two ways of wiring: automatic wiring and interactive wiring. Before automatic routing, you can use interactive pre-wired lines that require more stringent requirements. The edges of the input and output ends should avoid adjacent parallel to avoid reflection interference. Grounding should be added when necessary. The wiring of two adjacent layers should be perpendicular to each other, and parasitic coupling is easy to occur in parallel.

The routing rate of automatic routing depends on a good layout. The wiring rules can be preset, including the number of bending of the traces, the number of vias, the number of steps, etc. Generally, the exploration warp is first performed, and the wiring is quickly Short-line communication, then labyrinth wiring, first optimize the routing path of the wiring to be clothed, it can disconnect the laid line as needed. Try to re-route again to improve the overall effect.

For the current high-density PCB design, it has been felt that the through-hole is not well adapted. It wastes a lot of valuable wiring channels. To solve this contradiction, blind hole and buried hole technology have emerged, which not only completes the function of the via hole. It also saves a lot of wiring channels to make the wiring process more convenient, smoother and more perfect. The PCB board design process is a complicated and simple process. To master it well, it also needs extensive electronic engineering design. People go to their own experience, in order to get the true meaning.

1, power, ground processing

Even if the wiring in the entire PCB board is completed very well, the interference caused by the inconsistency of the power supply and the ground line will degrade the performance of the product, and sometimes even affect the success rate of the product. The wiring of the ground wire should be taken seriously, and the noise interference generated by the electricity and ground wires should be minimized to ensure the quality of the products.

For every engineering engineer engaged in the design of electronic products, the reason for the noise between the ground and the power line is understood. Only the reduced noise suppression is described:

It is well known to add a decoupling capacitor between the power supply and the ground.

Try to widen the power supply and ground line width. It is better to ground the ground line than the power line. Their relationship is: ground line > power line > signal line. Usually the signal line width is 0.2~0.3mm, and the finest width is up to 0.05~0.07mm, power cord is 1.2~2.5 mm

For the PCB of the digital circuit, a wide ground wire can be used to form a loop, that is, a ground net is used for use (the ground of the analog circuit cannot be used in this way), and a large-area copper layer is used for the ground line, and the printed circuit board is not used. The place is connected to the ground as a ground wire. Or made into a multi-layer board, power supply, ground line each occupy a layer.


2. Co-processing of digital circuits and analog circuits

Many PCBs are no longer single-function circuits (digital or analog circuits), but are composed of a mixture of digital and analog circuits. Therefore, it is necessary to consider the interference between them when wiring, especially on the ground. interference.

The frequency of the digital circuit is high, and the sensitivity of the analog circuit is strong. For the signal line, the high-frequency signal line is as far as possible away from the sensitive analog circuit device. For the ground line, the whole human PCB has only one node to the outside, so The problem of processing the number and the common mode must be carried out inside the PCB, and the digital ground and the analog ground inside the board are actually separated from each other, but only at the interface where the PCB is connected to the outside (such as a plug, etc.). The digital ground is short-circuited with the analog ground. Please note that there is only one connection point. There is also no common ground on the PCB, which is determined by the system design.


3. The signal line is laid on the electrical (ground) layer.

In the wiring of multi-layer printed boards, since there are not many lines left in the signal line layer, the addition of layers will cause waste and increase the workload for production, and the cost will increase accordingly. To resolve this contradiction, consider wiring on the electrical (ground) layer. First consider the power plane, followed by the ground plane. Because it is best to preserve the integrity of the formation.


4. Treatment of connecting legs in large-area conductors

In a large area of grounding (electricity), the legs of common components are connected to them, and the treatment of the connecting legs needs to be comprehensively considered. In terms of electrical performance, the pads of the component legs are perfectly connected with the copper surface, but There are some hidden dangers in the welding assembly of components. For example, 1 welding requires high-power heaters. 2 It is easy to cause virtual solder joints. Therefore, taking into account electrical performance and process requirements, a cross-shaped pad is formed, which is called heat shield. Commonly known as the thermal pad (Thermal), in this way, the possibility of creating a solder joint due to the excessive heat of the cross section during soldering is greatly reduced. The processing of the grounding (ground) leg of the multilayer board is the same.


5, the role of the network system in the wiring

In many CAD systems, the wiring is determined according to the network system. The mesh is too dense, although the path is increased, but the step is too small, the data volume of the field is too large, which inevitably has higher storage space for the device. The requirements, but also the computing speed of the computer-like electronic products have a great impact. Some of the paths are invalid, such as occupied by the pads of the component legs or occupied by the mounting holes, fixed holes, etc. Too thin, too few paths have a great impact on the routing rate. Therefore, there must be a sparse and reasonable grid system to support the wiring.

The distance between the legs of the standard components is 0.1 inches (2.54mm), so the basis of the grid system is generally set to 0.1 inches (2.54 mm) or less than 0.1 inches of multiples, such as: 0.05 inches, 0.025 inches, 0.02 Inches, etc.


6. Design Rule Check (DRC)

After the wiring design is completed, it is necessary to carefully check whether the wiring design meets the rules set by the designer, and also to confirm whether the established rules meet the requirements of the printed board production process. The general inspection has the following aspects:


Line and line, line and component pad, wire and through hole, component pad and through hole, the distance between through hole and through hole is reasonable, whether it meets production requirements.

Is the width of the power and ground wires appropriate? Is there a tight coupling between the power supply and the ground (low wave impedance)? Is there a place in the PCB where the ground wire can be widened?

Whether the best measures are taken for the key signal lines, such as the shortest length, the protection line, the input line and the output line are clearly separated.

Whether the analog circuit and the digital circuit part have separate ground lines.

Whether the graphics (such as icons, and markers) added to the PCB will cause a signal short circuit.

Modify some undesired lines.

Is there a process line on the PCB? Does the solder mask meet the requirements of the production process, whether the solder mask size is appropriate, and whether the character mark is pressed on the device pad to avoid affecting the quality of the battery.

Whether the edge of the outer frame of the power supply layer in the multi-layer board is reduced, such as the copper foil of the power supply layer is exposed outside the board, which is likely to cause a short circuit. The purpose of this document is to explain the process of designing the printed board using the printed circuit board design software PowerPCB of PADS. And some precautions, design specifications for a working group's designers to facilitate communication and mutual inspection between designers.


First, the design process

PCB design flow is divided into six steps: netlist input, rule setting, component layout, wiring, inspection, review, and output.

1.1 Netlist input

There are two methods for netlist input. One is to use PowerLogic's OLE PowerPCB Connec ti on function. Select Send Netlist and apply OLE function to keep the schematic and PCB diagram consistent at all times, and minimize the possibility of error.

Another method is to load the netlist directly in the PowerPCB, select File->Import, and enter the netlist generated by the schematic.


1.2 Rule settings

If you have already set the PCB design rules in the schematic design stage, you don't need to set these rules anymore, because when you enter the netlist, the design rules have been entered into the PowerPCB with the netlist. If you modify the design rules, you must Synchronize the schematic to ensure that the schematic and the PCB are consistent. In addition to the design rules and layer definitions, there are some rules that need to be set, such as Pad Stacks, which need to modify the size of the standard vias. If the designer creates a new pad or via , must add Layer 25.


note:

PCB design rules, layer definitions, via settings, and CAM output settings have been created as default startup files. The name is Default.stp. After the netlist is entered, the power network and ground are assigned to the power and ground layers according to the actual design conditions. And set other advanced rules. Set all the rules. In PowerLogic, use the Rules F rom PCB function of OLEPowerPCB Connection to update the rule settings in the schematic to ensure that the schematic and PCB diagram rules are consistent.


1.3 Component layout

After the netlist is input, all the components will be placed at the zero point of the work area and overlapped. The next step is to separate these components and arrange them neatly according to some rules, ie component layout. PowerPCB provides two methods. , manual layout and automatic layout.


1.3.1 Manual layout

1. The structural dimensions of the tool printed board are drawn with the board outline.

2. Disperse the components (Dispe rs e Components), the components will be arranged around the edge of the board.

3. Move the components one by one, rotate them, place them inside the edge of the board, and arrange them neatly according to certain rules.


1.3.2 Automatic layout

PowerPCB provides automatic layout and automatic local cluster layout, but for most designs, the results are not ideal.

Not recommended.1.3.3 Precautions

a. The first principle of layout is to ensure the routing rate of the wiring. Pay attention to the connection of the flying line when moving the device, and put the devices with the connection relationship together.

b. Separate digital and analog devices and keep them as far away as possible

c. Decoupling capacitors as close as possible to the VCC of the device

d. Consider the future soldering when placing the device, not too dense

e. Increase the efficiency of the layout by using the Array and Union functions provided by the software.


1.4 wiring

There are two ways to route, manual routing and automatic routing. The power wiring provided by PowerPCB is very powerful, including automatic push, online design rule checking (DRC), and automatic routing is performed by Specctra's routing engine. Usually these two methods work together. Use, the common steps are manual - automatic - manual.


1.4.1 Manual wiring

1. Before auto-routing, first lay some important networks by hand, such as high-frequency clocks, main power supplies, etc. These networks often have special requirements for trace distance, line width, line spacing, shielding, etc. Other special packages, For example, BGA, automatic wiring is difficult to lay out rules, but also manual wiring.


2. After the automatic wiring, the wiring of the PCB should be adjusted by manual wiring.

1.4.2 Automatic Wiring

After the manual routing is completed, the remaining network is handed over to the autorouter from the cloth. Select Tools->SPECCTRA, start the interface of the Specctra router, set the DO file, press Continue to start the automatic routing of the Specctra router. If the cloth pass rate is 100, then you can manually adjust the wiring; if it is less than 100, it indicates that there is a problem with the layout or manual wiring, and you need to adjust the layout or manual wiring until all the connections are made.


1.4.3 Precautions

a. Power cord and ground wire should be as thick as possible

b. Decoupling capacitors should be directly connected to VCC

c. When setting the DO file of Specctra, first add the Protect all wires command to protect the line of the manual cloth from being redeployed by the autorouter.

d. If there is a hybrid power layer, the layer should be defined as Split/mixed Plane, split before wiring, and after the wire is finished, use Pour Manager's Plane Connect for copper cladding.

e. Set all device pins to hot pad mode by setting Filter to Pins, selecting all pins, modifying properties, and ticking the Thermal option.

f. Open the DRC option during manual routing, using Dynamic Route (Dynamic Route)


1.5 check

Items checked include Clearance, Connectivity, High Speed, and Plane. These items can be selected by Tools->Verify Design. If you set a high-speed rule, you must check it. Otherwise, you can Skip this item. Check for errors and you must modify the layout and routing.


note:

Some errors can be ignored. For example, some of the connectors' Outline are placed outside the board frame, and errors are detected when checking the spacing. In addition, each time the traces and vias are modified, the copper is re-copied.


1.6 Review

Review according to the "PCB checklist", including design rules, layer definition, line width, spacing, pads, via settings;

It is also important to review the rationality of the device layout, the wiring of the power supply and ground network, the wiring and shielding of the high-speed clock network, the placement and connection of the decoupling capacitors, etc. If the review fails, the designer must modify the layout and wiring. After passing the qualification, the reviewer and the designer sign separately.


1.7 Design output

The PCB design can be output to the printer or output light painting file. The printer can print the PCB layer by layer, which is convenient for designers and reviewers to check; the light painting file is handed over to the board manufacturer to produce the printed board. The output of the light painting file is very important. Related to the success or failure of this design, the following will focus on the notes on the output of the light painting file.

a. The layers to be output have wiring layers (including top layer, bottom layer, intermediate wiring layer), power layer (including VCC layer and GND layer), silk screen layer (including top screen printing, bottom screen printing), solder mask (including top solder mask) And underlying solder mask), in addition to generate drilling files (NC Drill)

b. If the power layer is set to Split/Mixed, select Routing in the Document item of the Add Document window, and use the Pour Manager's Plane Connect to laminate the PCB before each output of the lithography file; if set to CAM Plane, select Plane. When setting the Layer item, add Layer25 and select Pads and Viasc in Layer 25. In the Device Settings window (press Device Setup), change the value of Aperture to 199.

d. Select the Board Outline when setting the Layer for each layer.

e. When setting the layer of the silkscreen layer, do not select Part Type, select the top (bottom) and silkscreen layers of Outline, Text, Line

f. When setting the Layer of the solder mask, selecting the via hole means that no solder mask is added on the via hole, and the via hole is not selected to indicate the home solder mask, which is determined according to the specific situation.

g. When creating a drilling file, use the default settings of PowerPCB, do not make any changes.

h. After all the lithography files are output, use CAM350 to open and print. The designers and reviewers check the vias according to the “PCB checklist”. It is one of the important components of multi-layer PCB. The cost of drilling is usually occupied. PCB board costs 30 to 40. Simply put, each hole on the PCB can be called a via. In terms of function, the vias can be divided into two categories:


One is used as an electrical connection between the layers;

The second is used for the fixing or positioning of the device. If the process is in the process, these vias are generally divided into three types, namely, blind via, buried via, and through via. The holes are located on the top and bottom surfaces of the printed circuit board and have a certain depth for the connection of the surface lines and the underlying inner lines. The depth of the holes usually does not exceed a certain ratio (aperture). The buried holes are located in the printed circuit board. The connection hole of the layer, which does not extend to the surface of the circuit board. The above two types of holes are located in the inner layer of the circuit board, and are completed by a through hole forming process before lamination, and may overlap several times during the formation of the via hole. Inner layer.

The third type is called a through hole. This hole passes through the entire circuit board and can be used to realize internal interconnection or as a mounting hole for components. Since the through hole is easier to implement in the process and lower in cost, most of the printing is performed. The circuit board uses it instead of the other two types of vias. The vias described below are considered as through holes unless otherwise specified. From a design point of view, a via is mainly composed of two parts, one It is the middle drill hole, and the second is the pad area around the hole. See the figure below. The size of these two parts determines the size of the hole.

Obviously, in high-speed, high-density PCB design, designers always want the smaller the via, the better, so that more wiring space can be left on the board. In addition, the smaller the via, its own parasitic capacitance. The smaller the size, the more suitable for high-speed circuits. However, the reduction in the hole size also brings about an increase in cost, and the size of the via hole cannot be reduced indefinitely. It is subjected to drilling and plating. Process technology limitations: the smaller the hole, the longer it takes to drill, and the easier it is to deviate from the center position; and when the depth of the hole exceeds 6 times the diameter of the hole, there is no guarantee that the hole wall will be uniformly plated with copper. Now, the thickness of a normal 6-layer PCB board (through-hole depth) is about 50Mil, so the diameter of the drill hole that PCB manufacturers can provide can only reach 8Mil.


Third, the parasitic inductance of the via

Similarly, there are parasitic inductances in the vias with parasitic capacitance. In the design of high-speed digital circuits, the parasitic inductance of vias often causes more damage than parasitic capacitance. Its parasitic series inductance will weaken the bypass capacitor. Contribution, weakening the filtering effect of the entire power system. We can simply calculate the parasitic inductance of a via approximation using the following formula: L = 5.08h [ln(4h/d) 1] where L is the inductance of the via, h It is the length of the via, and d is the diameter of the center hole. It can be seen from the equation that the diameter of the via has less influence on the inductance, and the most influence on the inductance is the length of the via. The above example is still used. The inductance of the via can be calculated as: L=5.08x0.050[ln(4x0.050/0.010) 1]=1.015nH. If the rise time of the signal is 1ns, then the equivalent impedance is: XL=πL/ T10-90=3.19Ω. Such impedance can not be ignored in the presence of high-frequency current. It is important to note that the bypass capacitor needs to pass through two vias when connecting the power supply layer and the ground plane. The inductance will increase exponentially.


Fourth, the design of the via hole in the high speed PCB

Similarly, there are parasitic inductances in the vias with parasitic capacitance. In the design of high-speed digital circuits, the parasitic inductance of vias often causes more damage than parasitic capacitance. Its parasitic series inductance will weaken the bypass capacitor. Contribution, weakening the filtering effect of the entire power system. We can simply calculate the parasitic inductance of a via approximation using the following formula: L = 5.08h [ln(4h/d) 1] where L is the inductance of the via, h It is the length of the via, and d is the diameter of the center hole. It can be seen from the equation that the diameter of the via has less influence on the inductance, and the most influence on the inductance is the length of the via. The above example is still used. The inductance of the via can be calculated as: L=5.08x0.050[ln(4x0.050/0.010) 1]=1.015nH. If the rise time of the signal is 1ns, then the equivalent impedance is: XL=πL/ T10-90=3.19Ω. Such impedance can not be ignored in the presence of high-frequency current. It is important to note that the bypass capacitor needs to pass through two vias when connecting the power supply layer and the ground plane. The inductance will increase exponentially.


Through the above analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often have a large negative effect on the design of the circuit. In order to reduce the parasitic parasitics The adverse effects of the effect can be as far as possible in the design:

1. From the perspective of cost and signal quality, choose a reasonable size of the via size. For example, for a 6-10 layer memory module PCB design, a 10/20Mil (drill/pad) via is preferred. For some high-density small-sized boards, you can also try to use 8/18Mil vias. Under current technical conditions, it is difficult to use smaller-sized vias. For power or ground vias, consider using Large size to reduce impedance.

2, the two formulas discussed above can be drawn, the use of a thin PCB board is beneficial to reduce the two parasitic parameters of the via.

3. The signal traces on the PCB should not be changed as much as possible, that is, try not to use unnecessary vias.

4. The power and ground pins should be near the hole. The shorter the lead between the via and the pin, the better, because they will lead to an increase in inductance. At the same time, the power and ground leads should be as thick as possible to reduce the impedance. .

5. Place some grounded vias near the vias of the signal-changing layer to provide the most recent loop for the signal. You can even place a large number of redundant ground vias on the PCB. Of course, you need to be flexible in design. The via model discussed above is where each layer has pads, and sometimes we can reduce or even remove pads from certain layers. Especially if the via density is very large, it may result in In the copper layer to form a broken circuit of the partition circuit, in order to solve such a problem, in addition to moving the position of the via hole, we can also consider reducing the size of the via hole in the copper layer.