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2019

02/15

Analysis on the process of single chip interrupt processing

The interrupt processing can be divided into three phases: interrupt response, interrupt processing, and interrupt return.

Interrupt response

The interrupt response is the CPU's response to the interrupt source interrupt request, including the protection breakpoint and the entry address (usually called the vector address) that directs the program to the interrupt service routine.

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nterrupt response process

The interrupt response process includes protecting the breakpoint and redirecting the program to the entry address of the interrupt service routine. First, the interrupt system automatically generates a long call instruction (LACLL) through hardware, which will automatically push the breakpoint address into the stack protection (does not protect the contents of accumulator A, status register PSW and other registers), and then the corresponding interrupt The entry address loader counter PC (automatically executed by hardware) causes the program to go to the interrupt entry address and execute the interrupt service routine. MCS-51 Series MCU The entry address of each interrupt source is preset by hardware and is assigned as follows:

Interrupt source entry address


External interrupt      0 0003H


Timer T0 interrupt    000BH


External interrupt     1 0013H


Timer T1 interrupt   001BH


Serial port interrupt  0023H


In use, an absolute jump instruction is usually stored at these interrupt entry addresses to cause the program to jump to the start address of the user-scheduled interrupt service routine.

Interrupt return

Interrupt return means that after the interrupt service is finished, the computer returns to the original disconnected position (ie, the breakpoint) and continues to execute the original program. The interrupt return is implemented by the interrupt return instruction RE TI. The function of this instruction is to pop the breakpoint address from the stack and send it back to the program counter PC. In addition, it also informs the interrupt system that the interrupt processing has been completed and the priority status trigger is also cleared. In particular, be careful not to replace the "RETI" instruction with the "RET" instruction.


Removal of interrupt request

After the CPU responds to the interrupt request, it enters the interrupt service routine. Before the interrupt returns, the interrupt request should be removed. Otherwise, the interrupt will be repeated and cause an error. The MCS-51 interrupt source interrupt request cancellation methods are different, respectively:

1) Removal of timer interrupt request

For timer 0 or 1 overflow interrupt, the CPU automatically clears its interrupt flag bit TF0 or TF1 after responding to the interrupt, without taking other measures.

2) Removal of serial port interrupt request

For serial port interrupts, the hardware cannot automatically clear the interrupt request flag bits TI, RI after responding to the interrupt, and must be cleared by software in the interrupt service routine.

3) Removal of external interrupt request


External interrupts can be divided into edge-triggered and level-triggered.

For an edge-triggered external interrupt 0 or 1, the CPU automatically clears its interrupt flag bit IE0 or IE1 after responding to the interrupt, without taking other actions.