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2.5D heterogeneous and 3D wafer level stacking is reshaping the packaging industry

Stacking: A highly integrated alternative to Moore's Law

The slowdown in Moore's Law has opened the way for new inventions that meet the stringent requirements of industry megatrends. In the field of packaging, many semiconductor manufacturers prefer 2.5D and 3D stacking technology, and through-silicon via (TSV) is one of the earliest stacking technologies. After several years of development and attention to MEMS, it has finally entered many application areas. Today, 2.5D and 3D stacking technologies have become the only solution to meet the performance needs of today's artificial intelligence (AI) and data center applications. Stacking technology has been applied to a variety of hardware in the high, medium and low end markets, including 3D stacked storage, graphics processing units (GPUs), field programmable gate arrays (FPGAs), and CMOS image sensors (CIS).

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Hardware such as high bandwidth storage (HBM) and CMOS image sensors account for most of the revenue in the TSV market. The overall market size of stacking technology will exceed $5.5 billion in 2023, with a compound annual growth rate (CAGR) of 27% during this period. For now, the consumer market is the largest market segment with a market share of more than 65%. Paradoxically, this does not mean that the consumer market is the main driver of these technologies. In fact, high-performance computing (HPC) is the real driver of stacking technology, and will show the fastest growth rate between 2019 and 2023. The market share is expected to increase from 20% in 2018 to 40% in 2023. In terms of package revenue, this is equivalent to more than 6 times the revenue of 2018. Correspondingly, the consumer market share will decrease, while other markets such as automotive, medical and industrial will maintain their current market share.

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Packaging technology is booming from TSV to wafer level stacking

Since stacking technology competition is mainly concentrated between "TSV" and "TSV-less", Yole analyzes these two types of technologies in this report.

For the current high-end market, the most popular 2.5D and 3D integration technologies on the market are 3D stacked storage TSVs and heterogeneous stacked TSV interposers. Chip-on-Wafer-on-Substrate (CoWos) technology has been widely used in high-performance computing applications. The new TSV technology will be available in 2019, which is based on Intel's Foveros (based on "active" TSV interposer and 3D SoC technology with hybrid bonding and TSV interconnect (possible) technology. The emergence of Foveros shows that although "TSV" has been challenged by "no TSV" technology, manufacturers still have confidence in it.

We cannot ignore the rise of "no TSV" technology in the market. These innovations can be divided into two groups, "with substrate" and "embedded in substrate." Embedded Multi-Chip Interconnect Bridge (EMIB) technology has been commercialized as one of the "embedded substrate" groups with deeper Si bridges in the substrate. Other substrate technologies are also under development, but are still not available, such as integrated thin film high density organic packaging (I-THOP) and flip chip-embedded interposer carrier (FC-EIC).

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On the left is the industry standard 2.5D package chip, on the right is the Intel EMIB package chip. Source: Intel Embedded Multi-Chip Interconnect Bridge (EMIB)

The "substrate-type" technology is also used for TSV replacement, such as the integrated fan-out package (InFO) on the substrate, which is widely used in Apple's processors. In addition, redistribution layer (RDL) interposer technology is currently under development and is expected to be available in 2020. Finally, it should be noted that the Fan Out Chip on Substrate (FOCoS) was developed and commercialized in 2016, but it seems that there are not many orders.

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Hybrid bonding technology bridges the two main technology categories "TSV" / "No TSV". The unique feature of this technology is that it can simultaneously become a challenger and supporter of TSV technology. Since 2016, it has been used in CMOS image sensors for smartphones, and in the near future it will be an interconnect solution for integrated storage and 2.5D high-end markets.

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Who is supporting and investing in stacking technology? Different market participants want to have a foothold in the growing $5.5 billion stacking market. There are currently four business models competing in the stacking business: foundries, integrated device manufacturers (IDMs), outsourced semiconductors Test vendors (OSAT) and IP vendors. According to Mamms Consulting, wafer foundries such as TSMC, UMC, and GlobalFoundries dominate TSV heterogeneous stacking because they have the ability to produce their own interposers. Intel, with "Foveros" technology, is the only IDM that is trying to compete in this space.

For 3D stacked storage, the competition is mainly between IDM "Big Three" Samsung, SK Hynix and Micron, which will continue to dominate the stacked storage market.

At the same time, 3D SoC is a foundry technology, and it is likely that only one foundry will produce it to ensure high yields and control risks. In this regard, TSMC is ahead of the grid in the competition for time to market.

For "no TSV" technology, competition is mainly between foundries, IDMs, OSATs and substrate manufacturers. Manufacturers such as Samsung, Intel and TSMC are involved in the development of "have" and "no" TSV technologies. In 2016, OSAT giant ASE introduced FOCoS technology to the market, and other manufacturers such as Amkor have developed suitable technologies, but are still waiting for orders.

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