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2019

04/09

SEMICON China 201930475;'IC23553;' 27979;'21457;' 24577;

SEMICON China 2019 has come to an end, during which IC design, manufacturing, sealing, equipment, materials and other industry chain suppliers from home and abroad gathered in Shanghai for a grand gathering. TrendForce Chinaconsulting will analyze the development trend of IC sealing industry in China from IC packaging technology and testing equipment.

Wafer-level advanced packaging technology is the technology goal of major sealing manufacturers

This year, the three major sealing and measuring factories in mainland China and Crystal Science and Technology in the N5 Pavilion of SEMICON Shanghai Exhibition are all exhibited. The key points of the major sealing and measuring factories are to show the diversity and completeness of the packaging technology possessed by the enterprises themselves, especially the wafer-level packaging technology and SiP technology. With the wafer-level advanced packaging capacity, they have become the technical competition target of the professional IC sealing and testing industry (OSAT). SiP packaging technology reflects the customization ability of potential customers.

From the point of view of technical characteristics, wafer-level packaging technology can be divided into FIWLP (Fan-In WLP Fan-in wafer-level packaging) and FOWLP (Fan-Out WLP Fan-out wafer-level packaging). Compared with FI, FO can expand I/O bumping through the RDL layer to the peripheral of IC chip, without reducing Ball pitch too much while meeting the increase of I/O number.

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Figure 1 FIWLP and FOWLP schematics

At present, wafer-level packaging accounts for about 20% of the total advanced packaging (mainly Flip Chip, Embedded Die in Substrate, FIWLP, FOWLP, 2.5D/3D). Fan-in packaging devices are mainly WiFi/BT integrated components, transceivers, PMIC and DC/DC converters. The world's major participants include sunlight, silicon, long-term power technology, Texas instruments, Reliance and TSMC account for about 60% of the global FIWLP. 。 Fan-out packaging can be divided into low-density fan-out packaging (less than 500 I/O, more than 8um line width and line spacing) and high-density fan-out packaging. Low-density fan-out packaging is mainly used for basic frequency processor, power management chip, radio frequency transceiver, high-density fan-out packaging is mainly used for AP, memory and other chips with a large number of I/O connectors. Relatively speaking, there are fewer participants in fan-out wafer-level packaging, with about 85% of the world's share of long-term power technology, TSMC, security, sunlight and moonlight.

It is worth mentioning that after the introduction of eSiFO technology with its own IP characteristics, Huatian Technologies, a new fan-out packaging player, launched eSinC (Embedded System in Chip) technology at this year's SEMICON China New Technology Conference. ESinC technology also uses etching to form grooves on silicon substrates, putting different chips or components into grooves, interconnecting chips through high density RDL, forming fan-out I/O, and then making via last TSV to achieve vertical interconnection. ESinC can integrate devices of different functions, types and sizes in 3D direction.

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Figure 2 Huatian Technologies eSinC schematic diagram

With the increasing demand for high performance, small size, high reliability and ultra-low power consumption of electronic products in the future, wafer-level packaging will be driven to apply wafer-level packaging technology to more emerging market segments, such as 5G millimeter-wave devices, micro-electronics, ADAS automotive applications and so on, by virtue of its inherent, incomparable minimum package size and low cost (no carrier).

Regarding the development of wafer-level packaging in the future, TrendForce Chip Consulting believes that:

1) Proxy factories with advanced technology have the advantages of technology, talent and resources in the research and development of advanced packaging technology, so they will be dominated by Foundry factories in the future in high-density fan-out integration (especially in 3D integration), and TSMC will be the main leader; 2) OSAT and IDM will be the main ones in fan-in and low-density fan-out, and with the passage of time, they will enter. OSAT factories will become more and more, and enterprises will compete differently. 3) In order to further reduce packaging costs, many manufacturers are doing panel-based research and development. It is expected that panel-based technology will be released in SEMICON China in two years.

Advanced packaging is expected to drive domestic equipment to further improve the domestic rate

In this SEMICON China Exhibition on packaging equipment, the traditional packaging equipment is mainly international large-scale equipment, while in the advanced packaging field, the number of exhibitions by Chinese manufacturers is larger, including North Huachuang, Shanghai Microelectronics, Medium and Micro Semiconductors, Shengmei Semiconductor, etc. North Huachuang can provide UBM/RDL PVD for Flip Chip Bumping, FI, FO and 2.5D/3D packaging technology. High aspect ratio TSV etching, TSV PVD process equipment; Shanghai Microelectronics Show 500 series step projection lithography machine for advanced packaging; Shengmei Semiconductor has released advanced packaging copper throwing equipment and advanced packaging copper plating equipment.

In the production process of advanced packaging, lithography, etching machine, sputtering equipment and other front-end equipment will be used. However, compared with the front-end manufacturing equipment, the precision and resolution requirements of advanced packaging equipment are relatively low. Taking lithography as an example, the resolution of step lithography machine used in Shanghai microelectronics for advanced packaging is about one tenth of the resolution of lithography machine used in front-end manufacturing.

According to Jibang Consulting Statistics, China's advanced packaging sales in 2018 amounted to 17.92 billion yuan, accounting for 8.9% of China's total sealed sales in 2018, which is much lower than the global advanced packaging proportion of 30%. In the future, China's advanced packaging will have a huge growth space. While Chinese equipment manufacturers continue to develop front-end equipment, they will cut into the rear-end equipment with low precision and resolution, which will further drive domestic equipment. A great opportunity to increase the domestic production rate.

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Figure 3 Equipment and Major Manufacturers for Fan-out Wafer-level Packaging

It is difficult for domestic testing machine and equipment manufacturers to share in the topics related to AI and 5G emerging industries for the time being.

At this exhibition, Advantest and Teradyne, the leading international testing machine companies, introduced advanced testing solutions in AI, 5G and other emerging industries. Among them, Edwan V93000 can be expanded platform, which has the functions of 1.6 Gbps data transmission rate per foot, active temperature control (ATC), etc. It uses the latest IC testing solutions and services to support A.C. I technology; Teradyne focuses on the introduction of AI and 5G testing machine US60G up to 60Gbps serial interface testing.

At present, the global integrated circuit FT testing machine is mainly in the hands of American and Japanese manufacturers. Terida, Kexiu and Edwan of Japan account for about 80% of the global market share of FT testing equipment. Through years of research and accumulation, Chinese local enterprises such as Changchuan Science and Technology and Beijing Huafeng Measurement and Control have begun to realize import substitution in the fields of analog/digital analog testing and discrete device testing. However, mature products and market breakthroughs have not yet been formed in the areas of SoC and storage which require high testing requirements, and are basically only used in the low-end testing fields of Chinese local sealing and testing plants.

Nowadays, in the emerging industries such as AI and 5G, chip integration is higher and test machine modules are more. With the advantages of technology, talent and market, international oligarchs have a strong trend. At the same time, because the SoC chip testing field involves the comprehensive application of algorithms, hardware design, structural design and other fields of technology, and achieves multi-functional comprehensive testing on a single platform and effectively controls the testing time, there are very high technical barriers. Local enterprises start late, and need to carry out overall system research and development through independent innovation to achieve domestic production in the high-end testing field. The road is far from being blocked.