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2019

07/17

From design to packaging, how are semiconductors made?

1. Complex and tedious chip design process


The process of chip manufacturing is just like building a house with Lego. After wafers are used as the foundation and then stacked layer by layer, the necessary IC chips can be produced (these will be introduced later). However, without a design, it is useless to have the ability to re-construct. Therefore, the role of architect is very important. But who is the architect in IC design? This article will introduce IC design next.


In the IC production process, IC is mostly planned and designed by professional IC design companies, such as Lianfeng Branch, Qualcomm, Intel and other well-known large factories. They all design their own IC chips to provide different specifications and efficiency chips for downstream manufacturers to choose. Because IC is designed by the factories themselves, IC design relies heavily on the technology of engineers. The quality of engineers affects the value of an enterprise. However, what steps do engineers take in designing an IC chip? The design process can be simply divided into the following steps.

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Design the first step, set goals


In IC design, the most important step is specification. This step is like deciding how many rooms and bathrooms to use before designing a building, what building codes to abide by, and designing after all the functions are determined, so that no additional time is needed for subsequent modifications. IC design also needs to go through similar steps to ensure that there are no errors in the design of the chip.


The first step of specification formulation is to determine the purpose and effectiveness of IC and to set the direction of IC. Next is to see which agreements to comply with, such as wireless network card chips need to comply with the specifications of IEEE 802.11, otherwise, the chip will not be compatible with the products on the market, making it unable to connect with other devices. Finally, it establishes the implementation method of this IC, divides different functions into different units, and establishes the method of linking different units, so as to complete the specification formulation.


After the specifications are designed, the details of the chip design follow. This step is like a preliminary record of the building plan, the overall outline will be drawn out, easy to follow-up mapping. In IC chips, hardware description language (HDL) is used to describe the circuit. The commonly used HDL includes Verilog, VHDL, etc. It is easy to express an IC function by code. The next step is to check the correctness of the program's functionality and continue to modify it until it meets the desired functionality.

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Verilog example of 32 bits adder


With computers, everything becomes easier.


With a complete plan, the next step is to draw a blueprint for the design of the plane. In IC design, the step of logic synthesis is to put the definite HDL code into EDA tool, so that the computer can convert HDL code into logic circuit and produce the following circuit diagram. Afterwards, it is determined repeatedly whether the design of the logic gate meets the specifications and is modified until the function is correct.

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Result of Control Unit Composition


Finally, the synthesized code is put into another set of EDA tools for circuit layout and winding (Place and Route). After continuous detection, the following circuit diagram will be formed. In the picture, you can see different colors such as blue, red, green and yellow, each of which represents a light mask. As for how to use the hood?

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Commonly used calculus chip - FFT chip, completing circuit layout and winding results

Layers of masks, stacking a chip

First of all, it is known that an IC will produce multiple optical masks, which have different tasks for each layer. The following is a simple example of the optical mask. Take CMOS, the most basic component in the integrated circuit, as an example. CMOS is called Complementary Metal - oxide - semiconductor, which combines NMOS and PMOS to form CMOS. As for what is Metal Oxide Semiconductor (MOS)? This widely used component in chips is difficult to explain, and it is difficult for the general reader to understand, so there is no more detail here.


In the following figure, the left side is a circuit diagram formed by circuit layout and winding. It is known in the front that each color represents a light mask. On the right is the way each mask is spread out. Manufacturing is to start from the bottom, follow the method mentioned in the previous IC chip manufacturing, layer by layer, and eventually produce the desired chip.

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So far, we should have a preliminary understanding of IC design. As a whole, it is clear that IC design is a very complex profession. Thanks to the maturity of computer-aided software, IC design can be accelerated. IC design factories rely heavily on the wisdom of engineers. Each step described here has its own expertise and can be independently divided into several professional courses. For example, writing hardware description language requires not only familiarity with programming language, but also understanding how logic circuits operate and how to convert required algorithms into processes. How to convert programs into logic gates by synthesizing software and so on.


2. What is a wafer?


In the semiconductor news, we always mention wafer factories marked by size, such as 8-inch or 12-inch wafer factories. However, what exactly is the so-called wafer? What part does 8-inch mean? What is the difficulty in producing large wafers? The most important foundation of semiconductor is described step by step below. What is a wafer?


Wafer is the basis of making all kinds of computer chips. We can analogize chip manufacturing to building a house with Lego building blocks. By stacking one layer after another, we can complete the desired shape (i.e., all kinds of chips). However, if there is no good foundation, the house built will be crooked, not their own desire, in order to make a perfect house, it needs a smooth foundation. For chip manufacturing, this substrate is the wafer that will be described next.

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First of all, let's recall that when we were young, when we were playing Lego, there would be a small circular projection on the surface of the building blocks. With this structure, we could firmly overlap the two blocks without using glue. Chip fabrication, in a similar way, fixes subsequent atoms and substrates together. Therefore, we need to find the surface of the neat substrate to meet the requirements of subsequent manufacturing.


In solid materials, there is a special crystal structure - Monocrystalline. It has the characteristics of atoms closely arranged one after another, and can form a flat atomic surface. Therefore, the use of single crystal wafers can meet the above needs. However, how to produce such materials, there are two main steps, namely, purification and crystallization, after which such materials can be completed.

How to Make Single Crystal Wafers


Purification is divided into two stages. The first step is metallurgical purification. This process mainly involves adding carbon and converting silicon oxide into more than 98% pure silicon by redox. Most metals, such as iron or copper, are refined in such a way as to obtain sufficient purity of metals. However, 98% is still not enough for chip manufacturing, which still needs further improvement. Therefore, the Siemens process will be further used for purification, so that the high purity polycrystalline silicon required for semiconductor manufacturing will be obtained.

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Silicon Column Manufacturing Process (Source: Wikipedia)


Next, the step of pulling crystal. First, the high purity polycrystalline silicon obtained above is melted to form liquid silicon. Later, the seed of a single crystal contacts the surface of the liquid and slowly pulls up as it rotates. As for why single crystal silicon seed is needed, because the arrangement of silicon atoms is the same as that of people queuing up, and it will need the head of the line to let later people how to arrange correctly. Silicon seed is the important head of the line, so that later atoms know how to queue up. Finally, after the silicon atoms leaving the liquid surface solidify, the neatly arranged single crystal silicon pillars are completed.

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Single Crystal Silicon Column (Souse: Wikipedia)


However, what do 8 inches and 12 inches represent? They refer to the crystal pillars that we produce, which look like pencil-and-pencil rods, and whose surfaces are treated and cut into thin wafers. What's the difficulty in making large wafers?


As mentioned earlier, the process of making crystal pillars is like making cotton candy, rotating and forming at the same time. If you have made cotton candy, you should know that it is very difficult to make large and solid cotton candy, and the process of crystallization is the same, the speed of rotation and temperature control will affect the quality of the crystal column. Therefore, the larger the size, the higher the requirement of speed and temperature, so it is more difficult to make high quality 12-inch wafer than 8-inch wafer.


However, a whole silicon column can not be made into a substrate for chip manufacturing. In order to produce a piece of silicon wafer, a diamond knife is needed to cut the silicon column into a transverse wafer, which can be polished to form the silicon wafer needed for chip manufacturing. After so many steps, the fabrication of chip substrates is successful. The next step is the stacking of houses, that is, the fabrication of chips. How to make chips?

Layer-by-layer stacked chips

After introducing what a silicon wafer is, I also know that making IC chips is like building a house with Lego blocks, creating the desired shape by stacking one layer after another. However, there are quite a lot of steps to build a house, and IC manufacturing is the same. What are the steps to make IC? This article will introduce the process of IC chip manufacturing.


Before we begin, we need to understand what IC chips are. IC (Integrated Circuit) is named after IC, which combines the designed circuits in a stacked way. With this method, we can reduce the area required to connect the circuit. The following is a 3-D picture of IC circuit, from which we can see that its structure is like the beams and columns of a house, stacked layer by layer, which is why IC manufacturing is compared to building a house.

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The 3D profile of IC chip. (Source: Wikipedia)


From the 3D profile of IC chip in the figure above, the dark blue part at the bottom is the wafer introduced in the previous article. From this picture, we can see more clearly how important the role of wafer substrate in the chip is. As for the red and khaki parts, it is the place to be completed when IC is made.


First of all, here we can compare the red part to the lobby on the first floor of a tall building. The lobby on the first floor is the gateway of a house, where all the entries and exits are. It usually has more functions under the control of traffic. Therefore, compared with other floors, the construction will be more complex and require more steps. In IC circuit, this hall is the logic gate layer, which is the most important part of the whole IC. It is composed of a variety of logic gates to complete a fully functional IC chip.


The yellow part is like a common floor. Compared with the first floor, there will not be too complex structure, and each floor will not have too many changes in the construction. The purpose of this layer is to connect the logic gates of the red part. The reason why so many layers are needed is that there are too many lines to be connected together. Under the condition that a single layer cannot accommodate all the lines, it is necessary to lay more layers to achieve this goal. In this way, different layers of lines will be connected up and down to meet the needs of wiring.


Layer-by-layer construction, layer-by-layer structure


After knowing the structure of IC, we will introduce how to make it. Imagine that if we want to make fine drawings of paint spray cans, we need to cut out the graphic covering board and cover it on paper. Then spray the paint evenly on the paper. When the paint is dry, remove the shutter. After repeating this step, we can complete the neat and complex graphics. Manufacturing IC is stacked layer by layer by layer in a similar way.

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When making IC, it can be simply divided into four steps. Although the actual manufacturing process will be different and the materials used will be different, similar principles are generally adopted. This process is slightly different from painting. IC manufacturing is to first paint and then cover, while painting is to cover and then paint. Each process is described below.

Metal Sputtering: Sprinkle metal materials evenly on the wafer to form a thin film.


Coated photoresist: First, the photoresist material is placed on the wafer, and the structure of the photoresist material is destroyed by striking the beam on the unnecessary part through the optical mask (the principle of the optical mask is left to be explained next time). Then the damaged material is washed away with chemicals.


Etching technology: Silicon wafers without photoresist protection will be etched by ion beam.


Photoresist removal: Use the remaining photoresist to dissolve, so as to complete a process.


Finally, many IC chips will be completed on a wafer. Next, as long as the completed square IC chips are cut off, they can be sent to the packaging plant for packaging. As for what the packaging plant is, we need to explain later.

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3. What is the nanotechnology?

Samsung and TSMC are very hot in the advanced semiconductor manufacturing process. They both want to seize the opportunity in wafer manufacturing to win orders. They almost become the contention between 14 nanometer and 16 nanometer. However, what are the meanings of these two figures, and what part do they refer to? After reducing the manufacturing process, they will take the place in the future. What are the benefits and challenges? Here we will give a brief description of nanofabrication.


How fine is nanometer?


Before we begin, we need to understand what nanometer means. Mathematically, nanometer is 0.000000001 meters, but this is a rather poor example. After all, we can only see a lot of zeros after decimal point, but there is no real feeling. If you compare nail thickness, it may be more obvious.


The thickness of a nail is about 0.0001 meters (0.1 millimeters) when measured with a ruler. That is to say, try to cut the side of a nail into 100,000 lines, each of which is about the same as 1 nanometer, so you can imagine how small a nanometer is.


Knowing how small nanoparticles are, we also need to understand the purpose of the reduction process. The main purpose of reducing transistors is to insert more transistors into smaller chips so that the chips will not become larger because of technological advances. Secondly, it can increase the efficiency of the processor. Furthermore, reducing the size can also reduce power consumption. Finally, when the size of the chip is reduced, it is easier to plug into the mobile device to meet the needs of future thinning.


Then come back and explore what nanofabrication is. Take 14 nanometer as an example. Its fabrication process means that in the chip, the line can be as small as 14 nanometer. The figure below shows the appearance of traditional transistors as an example. The main purpose of reducing transistors is to reduce power consumption. However, which part of transistors should be reduced to achieve this goal?


The L in the lower left is what we expect to shrink. By reducing the gate length, the current can be traveled from Drain to Source in shorter paths (more detailed explanation will be given if you are interested in using Google to search with MOSFET).

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In addition, computers operate on 0 and 1. How to use transistors to satisfy this purpose? The way is to judge whether transistors have current flow. When a voltage is supplied at the Gate terminal (green box), the current will flow from the Drain terminal to the Source terminal. If no voltage is supplied, the current will not flow, thus 1 and 0 can be represented. (As for why 0 and 1 should be used as judgements, if you are interested, you can go to Chablin algebra. We use this method to make computers.)


Dimension reduction has its physical limitations


However, the process can not be reduced indefinitely. When we reduce the transistor to about 20 nanometers, we will encounter problems in quantum physics, which will make the transistor leakage and offset the benefits of reducing L. As a way to improve, you import the concept of FinFET (Tri-Gate), as shown in the figure above on the right. In Intel's previous explanations, it is known that the introduction of this technology can reduce leakage caused by physical phenomena.

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More importantly, this method can increase the contact area of Gate end and lower layer. In the traditional way (top left), the contact surface has only one plane, but after using FinFET (Tri-Gate) technology, the contact surface will become three-dimensional, which can easily increase the contact area, so that the Source-Drain end can be smaller while maintaining the same contact area, which is quite helpful to reduce the size.




Finally, it is why some people say that major factories will face considerable challenges when they enter the 10-nanometer process. The main reason is that the size of an atom is about 0.1 nanometer. In the 10-nanometer situation, there are less than 100 atoms in a single line, which is very difficult to fabricate, and as long as there is an atomic defect, such as in the manufacturing process. When atoms fall out or impurities occur in the process, unknown phenomena will occur, which will affect the yield of products.


If you can't imagine the difficulty, you can do a small experiment. On the table, use 100 beads to form a 10 x 10 square, and cut a piece of paper to cover the beads, then brush off the beads with a small brush, and finally make him form a 10 x 5 rectangle. In this way, we can know the dilemma faced by the major factories and how difficult it is to achieve this goal.


With Samsung and TSMC completing the production of 14 nanometer and 16 nanometer FinFETs in the near future, they both want to compete for the next generation of Apple's iPhone chips. We will see quite brilliant commercial competition, but also more power-saving, lightweight mobile phones. Thanks to the benefits of Moore's Law.


Tell you what encapsulation is


Packaging, the ultimate protection and integration of IC chips


After a long process, from design to manufacture, we finally got an IC chip. However, a chip is quite small and thin. If it is not protected outside, it will be easily scratched and damaged. In addition, because of the small size of the chip, it is not easy to place the chip on the circuit board manually without a larger shell. Therefore, the next step of this article is to describe the encapsulation.


At present, there are two kinds of common packaging, one is common in electric toys, black like centipede DIP packaging, and the other is common BGA packaging when purchasing boxed CPU. As for other packaging methods, there are PGA (Pin Grid Array; Pin Grid Array) or QFP (Plastic Square Flat Package) used in the early CPU, etc. Because there are so many encapsulation methods, the following will introduce DIP and BGA encapsulation.


Traditional packaging, lasting


First of all, we will introduce the Dual Inline Package (DIP). From the figure below, we can see that the IC chip with this package will look like a black centipede under the foot of the double-row connection. This packaging method is the earliest IC packaging technology. It has the advantage of low cost and is suitable for small size and does not need to be connected. Too many lines of chips. However, because plastic is mostly used, the heat dissipation effect is poor, which can not meet the current requirements of high-speed chips. Therefore, most of the encapsulated chips are durable chips, such as OP741 in the figure below, or IC chips with less speed and smaller chips and fewer holes.

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The IC chip on the left is OP741, which is a common voltage amplifier. On the right is its profile. The package connects the chip to the Leadframe with gold wire. (Source: left Wikipedia, right Wikipedia)


As for Ball Grid Array (BGA) packaging, compared with DIP, the packaging volume is smaller and can be easily put into smaller devices. In addition, because the socket is under the chip, it can accommodate more metal sockets than DIP, which is quite suitable for chips that need more contacts. However, the cost of using this packaging method is higher and the connection method is more complex, so it is mostly used in high unit price products.

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The left picture shows the chip packaged in BGA. The right one is a BGA schematic diagram using cladding package. (Source: Wikipedia on the left)

The rise of mobile devices, new technologies leap onto the stage

However, using these packaging methods will consume a considerable amount of volume. For example, mobile devices, wearing devices and so on, need quite a variety of components. If each component is encapsulated independently, it will take a lot of space to assemble. So there are two ways to meet the requirements of reducing volume, namely SoC (System On Chip) and SiP (System In Packet).


SoC is a term that can be found in many financial magazines when smart phones are just emerging. But what is SoC? Simply speaking, IC with different functions is integrated into a chip. With this method, not only the size of the chip can be reduced, but also the distance between different ICs can be reduced, and the computing speed of the chip can be improved. As for the fabrication method, in the IC design stage, each different IC is put together, and then through the previously introduced design process, a mask is made.

However, SoC is not only good, it requires a lot of technical cooperation to design a SoC. When IC chips are encapsulated separately, each has its own external protection, and the distance between IC and IC is relatively long, so there is no interaction interference. But when all the ICs are packaged together, it's the beginning of the nightmare. IC design factory should change from the original simple design IC to the IC that understands and integrates various functions, and increase the workload of engineers. In addition, there will be many situations, such as high-frequency signal of communication chip may affect IC of other functions.


In addition, SoC also needs IP (intellectual property) authorization from other vendors in order to put the components designed by others into SoC. Because making SoC requires the design details of the whole IC to make a complete optical mask, which also increases the design cost of SoC. Perhaps some people will question why not design a new IC by themselves, because designing various ICs requires a lot of knowledge related to the IC. Only a company with a lot of money like Apple can budget top engineers from well-known enterprises to design a new IC. It is more cost-effective to design a new IC through cooperative authorization than to develop it by itself. 。


A compromise, SiP


As an alternative, SiP leaps onto the stage of integrated chips. Unlike SoC, it purchases individual IC's, encapsulates these IC's at the last time, thus reducing the IP authorization step and greatly reducing the design cost. In addition, because they are independent IC, the degree of interference between them is greatly reduced.

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Apple Watch uses SiP technology to encapsulate the entire computer architecture into a chip, which not only meets the desired performance, but also reduces the size, allowing the watch to have more space discharge batteries. (Source: Apple's official website)


The most famous product using SiP technology is Apple Watch. Because Watch's internal space is too small to use traditional technology, and SoC's design cost is too high, SiP is the first choice. SiP technology can not only reduce the volume, but also shorten the distance between IC, which is a feasible compromise. The following is the structure of the Apple Watch chip. You can see that a considerable number of ICs are included in it.

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The internal configuration diagram of SiP-packaged S1 chip in Apple Watch. (Source: chipworks)


After completing the package, we need to enter the testing stage. At this stage, we need to confirm whether the packaged IC is functioning properly. If it is correct, it can be shipped to the assembly plant to make the electronic products we see. So far, the semiconductor industry has completed the whole production task.