After entering the 14nm / 16nm process, the semiconductor process is most often referred to as a FinFET (FinFET). Its appearance satisfies the process manufacturing between 7nm and 14nm. However, after entering smaller 5nm or even 3nm, the FinFET process has been difficult to meet the manufacturing needs of semiconductor chips, and the industry is also researching new-generation transistors.
To this end, several major fabs are accelerating the 5nm process on the market, but now customers must decide whether to design their next chip around the current transistor type or move to a different chip with 3nm and above.
The decision involves extending the current FinFET to 3nm or implementing a new technology called GAA FET at the 3nm or even 2nm node. Surround gates, which have evolved from FinFETs, provide better performance, but these new transistors are difficult to manufacture, expensive, and the migration process can be difficult. On the plus side, the industry is developing new etching, patterning, and other technologies that will pave the way for these nodes.
The delivery time of these GAA FETs is determined by the major fabs. Both Samsung and TSMC are using FinFETs to produce 7nm processes. They will use FinFETs to mass-produce 5nm processes later this year and launch various half-node products around 5nm. This will increase speed and power.
However, Samsung plans to launch a GAA transistor called a nanosheet FET on a 3nm process sometime next year or 2022. At the same time, TSMC plans to first introduce FinFETs on a 3nm process. Analysts and equipment suppliers said that TSMC will introduce GAA in the full-gate structure at a later stage of 3nm or 2nm.
For new technologies, Qu Jianzhong, founder of the Taiwan Intellectual Property Expert Community, introduced that field effect transistors (FETs) are the most basic electronic components and are the smallest units of digital signals. It's a digit in the computer. The electrons flow in and out, and a gate switch controls the electrons to represent 1 or non-conductors to represent 0. Scientists made it on a silicon wafer.
"Process node" represents the "average length" of the gate, which will decrease with the progress of process technology. After the transistor was shrunk to less than 14nm, the original technology could not meet the needs of 14nm products. Only then did Professor Hu Zhengming's "fin-type field effect transistor (FinFET)". Polar field effect transistor. "
However, TSMC is still evaluating its 3nm process plan, and TSMC will soon disclose its 3nm plan, which may change at any time. Nevertheless, TSMC's move to expand FinFETs to 3nm is logical. The transfer to a new transistor may cause potential interference to customers. But in the end, FinFET will lose its advantages, and TSMC will have no choice but to turn to gate-all-around.
Other companies are also developing advanced processes. Intel is stepping up research and development at 10nm and 7nm. (Intel's 10nm process is similar to the fab's 7nm process) At the same time, SMIC is developing a 10nm / 7nm process to improve the 16nm / 12nm FinFET.
All advanced processes are expensive, and not all chips require 3nm or other advanced processes. In fact, rising costs are prompting many to explore other options. Another way to gain expansion is to place advanced chips in a package, for which some companies are developing advanced package types.
Is the scaling really over?
The chip is composed of three parts: a transistor, a node, and an interconnection line. Transistors act as device switches. Today, advanced chips have as many as 35 billion transistors.
The interconnect is located on top of the transistor and consists of tiny copper wires that carry electrical signals from one transistor to another. The transistors and interconnect lines are connected by a layer called the center line (MOL) layer. The middle layer uses a series of tiny contact structures to connect independent transistors and interconnects.
The traditional integrated circuit expansion design method is to reduce the transistor size of each process node and package it on a single chip.
To this end, chip makers introduce a new process technology every 18 to 24 months with higher transistor density. Each process has a numeric node name. Initially, the node name was related to the transistor gate length.
At each node, the chip maker increased the size of the transistor by a factor of 0.7, increased performance by 40% and reduced area by 50% at the same power. So, chip scaling makes new electronics more versatile.
This formula works as chip makers move along different process nodes. But a huge twist occurred at 20nm, and traditional 2D planar transistors lost power. Since 2011, chip makers have turned to FinFET, which is a 3D-like structure with better performance and lower leakage, enabling them to expand their devices.
However, FinFETs are more expensive to manufacture, leading to a surge in process R & D costs. So now the rhythm of a complete node has been extended from 18 months to 30 months, or even longer.
At the advanced node, Intel followed the trend of reducing transistor size by 0.7x, but at 16nm and 14nm, others began to break away from traditional methods and relax metal spacing. "Previously, the use of node names was related to the specified metal spacing," "At some point, we started to deviate from the spacing and focus more on the next node and feature size."
At that time, the node names became ambiguous and were no longer associated with any transistor specification. Gartner analyst Samuel Wang said: "The definition of node is becoming increasingly misleading and meaningless. For example, between 5nm or 3nm, no single geometry is actually a true 5nm or 3nm. In addition The commonality of processes between suppliers is greatly reduced. For the same node, TSMC and Samsung perform differently, and of course they are different from Intel. "
The expansion speed of advanced nodes is also slowing down. According to IC Knowledge and TEL research, in general, the 7nm foundry process has a polycrystalline silicon pitch CPP of 56nm to 57nm and a metal wiring pitch of 40nm. At 5nm, the CPP is approximately 45nm-50nm and the metal pitch is 26nm. CPP is a key transistor measurement used to measure the distance between source and drain contact points. It is reported that Samsung recently launched a high-profile 5nm, and is expected to be mass-produced in the first half of 2020. Compared with its 7nm, Samsung's 5nm FinFET technology has a 25% increase in speed, a 20% reduction in power consumption and a 10% increase in performance compared to 7nm.
In addition, the price / performance advantage no longer follows the same curve, prompting many to wonder if Moore's Law has come to an end.
In fact, Moore's Law is not a real law, but an observation. It has become a self-fulfilling prophecy, pushing the semiconductor industry forward. As the cost of multiple patterns and EUV increased, the economic aspects of Moore's Law began to decline. Douglas Guerrero, senior technical expert at Brewer Technologies, said: "The increase in computing power will appear in new designs and architectures, but this is not scalable. This means that future chips will increase computing power, but costs may not Falling at a past rate. "
For zooming, it doesn't completely disappear. Artificial intelligence, servers and smartphones are driving demand for faster chips on advanced nodes. D2S chief executive Aki Fujimura said that some people also believe that the world has no way to handle faster calculations beyond novel applications. "Today, for the IoT, low cost, good enough performance and integration outweighs more and higher computing density. But we need faster transistors to make more efficient, lower power, and can accommodate More transistor chips. "
Obviously, not all needs require advanced nodes, because mature process chip demand is strong. Jason Wang, Co-President of UMC, said: "These new products include RF IC and OLED driver chips used in 5G smartphones, as well as power management chips designed for computing and solid state drive applications."
At the same time, in terms of chip expansion, chip makers have followed the same process route for many years, using the same transistor types. In 2011, Intel switched to 22nm FinFETs, followed by 16 / 14nm fabs.
In FinFETs, current control is achieved by installing a gate on each of the three sides of the fin. FinFETs have two to four fins. Each fin has a different width, height, and shape.
Intel's first-generation FinFETs have a tail fin pitch of 22 nm at 22 nm and a tail height of 34 nm. Then, at 14nm, Intel's FinFET has a fin pitch and height of 42nm.
So Intel made the fins taller and thinner to fit the size of FinFETs. Nerissa Draeger, director of the forest research university project, explained in a blog post: "FinFET scaling reduces lateral dimensions to increase device density per unit area, while increasing fin height as a way to improve device performance."
At the 10nm / 7nm process, chip makers used the same approach to extend FinFETs. In 2018, TSMC introduced the first 7nm FinFET chip, followed by Samsung. At the same time, Intel released 10nm chips last year, and they had previously postponed the release many times.
By 2020, competition in the wafer industry will become more intense. Samsung and TSMC are adding 5nm processes and various half-node processes. 3nm is under development.
But keep in mind that all processes are expensive. According to IBS, the cost of designing a 3nm product is about $ 500 million to $ 1.5 billion, and its process development cost is about $ 4 billion to $ 5 billion, and the operating cost of building a production line is about $ 15 billion to $ 20 billion . "Based on the same maturity, 3nm transistor costs are expected to be 20% to 25% higher than 5nm," said IBS's Jones. "Compared to 5nm FinFETs, expected 15% increase in performance and 25% reduction in power consumption.
Compared with 7nm, Samsung's 5nm FinFET technology provides up to 25% logic area, reduces power consumption by 20%, and can improve performance by 10%.
Geoffrey Yeap, senior technical director of TSMC, said in a paper at a recent IEDM conference: In contrast, TSMC's 5nm FinFET process "provides a 15% speed increase at the same power. At the same power, the 7nm node's Reduced logic density by 30%. "
Chip makers are making a fuss about 7nm and 5nm processes. In order to shape the key characteristics of the chip, the two companies transitioned from traditional 193nm lithography to EUV lithography. Since EUV has a wavelength of 13.5nm, this process is simplified.
EUV cannot solve all the challenges of chip expansion. Regina Freed, general manager of pattern technology at Applied Materials, said in a blog post: "Solving these challenges requires multiple technologies that go beyond scalability, including the use of new materials, new embedded non-volatile memories and advanced New logic architectures, new approaches to deposition and etching, and packaging and chip design innovations. "
At the same time, Samsung and TSMC are preparing their 3nm processes. In the past, chip makers followed the same path, but according to today's roadmap, 3nm is where suppliers are parting ways.
Garner's Wang said: "3nm may have several different options, such as FinFET and surround gate, which provide customers with different combinations of cost, density, power and performance to meet their specific needs."
As mentioned earlier, Samsung will introduce nanosheet FETs at 3nm. TSMC is also developing such a chip, and it plans to expand FinFET to the next generation. "TSMC will launch 3nm process chips in the third quarter of 2021," said Jones of IBS. "TSMC's surround gates will be launched around 2022 or 2023."
This is where foundry customers must weigh various cost and technology trade-offs. Expanding FinFETs seems to be a safer approach. "Many customers see TSMC as a low-risk supplier."
However, the surrounding gate provides some more performance. Jones said: "Compared with 3nm FinFET, 3nm surround gate has lower threshold voltage and may reduce power consumption by 15% to 20%." "But the performance difference may be below 8% because MOL and BEOL are the same of."
However, it should be noted that the back end of line (BEOL) process and MOL are the bottlenecks of advanced chips. Contact resistance is a problem in MOL.
BEOL is to establish several layers of conductive metal wires, and the metal wires of different layers are connected by columnar metals. The interconnect becomes tighter at each node, causing a resistor-capacitor (RC) delay in the chip. FinFETs and surround gates are different transistor types, but they are likely to use similar copper interconnection schemes at 3nm. RC delay is an issue for both transistors.
There are other challenges as well. When the fin width reaches 5nm, FinFETs will lose power. 5nm / 3nm FinFETs are breaking these limits.
In addition, a 3nm FinFET may consist of one fin, while other nodes may have two or more fins. Naoto Horiguchi, Imec's director of CMOS device technology: "Single fins must have sufficient handling flexibility. In order to extend FinFETs to N3, we need a special technology to enhance single fin power and / or reduce back-end parasitics."
One way to extend FinFETs to 3nm is to move the germanium material to the p-channel. 3nm FinFETs with high mobility channels will provide performance improvements, but there are some integration challenges.