First, high-end electronic products have a high number of I / O interfaces and a large volume
With the rapid development of global electronic terminal products, whether it is mobile phone/wireless communication applications, consumer electronic applications or high-speed computing applications, electronic products can be observed towards high integration trends, the higher the performance and multi-functional products, in addition to accompanying The higher the number of I/Os in a semiconductor chip, the higher the number of chips required, and the larger the area of the entire packaged chip.
Figure 1: I/O number and area relationship of packaged wafers for electronic applications. Source: Yole(2017/02)
Second, the terminal products promote the evolution of packaging technology
When the terminal products are developed from handheld products, IoT consumer products, and automotive electronics to high-speed computing processors, the complexity of the product is increasing, and the chip packaging method that can be selected is gradually limited. Because high-performance products are equipped with advanced process chips and high integration (thin line width and wide line spacing) packaging technology, high-integration packaging technology is often accompanied by Low Yield Issue, so high-performance products The choice of packaging technology and even the practitioners who can provide this process technology are rare. Most packagers are also worried that the low package yield will cost a lot of expensive chips. This is a response to today's high-end 2.5D interposer. Most of the packaging is carried out at the fab, because the fab has the ability to provide chips, which is superior to the professional packaging and testing industry.
Figure 2: End products drive the evolution of packaging technology. Source: Amkor(2017/09)
Most of the advanced packaging technologies have chip integration capabilities, such as the current flip chip packaging technology with the largest volume or output value, or the rapid development of fan-out and 2.5D/3D packaging technology, and its annual production value from 2015 to 2021. The compound growth rate is as high as 49% and 43%, respectively. Relatively, the 5% annual compound growth rate of the flip chip package is inferior, which also reflects the fact that the flip chip package has the integration degree or the price. Technical bottlenecks, so the demand for high-bandwidth and high-speed computing electronics drives fan-out packages and even higher-order 2.5D/3D packages.
Figure 3: Trends in production value and annual compound growth rate of advanced packaging technology. Source: Yole (2018/03)
Flip Chip technology originated in the 1960s. It was originally developed by IBM on the mainframe, and the fan-out package technology was mainly derived from Starcom Jinpeng in 2008 with STMicroelectronics (( STMicroelectronics)), Infineon (Infineon) agreement to develop a new generation of eWLB technology based on Infineon's first generation of Wafer-Level Ball Grid Array (eWLB) technology The time-course and the drop of equipment and equipment lead to the development of the fan-out package, which is lagging behind the flip-chip package for a long time. One of the main devices used in the flip chip package is the panel-level carrier process, that is, the winding layer is the carrier process. Single or multiple wafers can be integrated on the carrier board by flip chip or wire bonding, but the line width of the carrier is less than 10/10 um. On the other hand, fan-out Although the development time of the package is shorter than that of the flip chip package, the process is mainly performed in wafer level packaging equipment. The winding layer is mainly a thin film process, so it has a high density line width (Line/). Space<8/8 um) The advantages of the process, only the current main Fan-out wafer packages (Single die fan-out) mainly, the yield is still highly challenging redistribution layer (RDL) in a fan-out package carried out in a multi-chip integration process.
Figure 4: Comparison of flip chip and fan-out packages. Source: Yole; ITRI IEK (2018/03)
Today's flip chip packaging technology is more mature than fan-out package technology, many flip chip package area is more than 15*15mm^2, and with hundreds of I/O numbers, and wafer integrated flip chip package (FCBGA; Flip Chip) Ball Grid Array) is more than 55*55mm^2 or more, and the number of I/O is more than 3000. The fan-out package is still mainly based on a single chip package, and the package area is less than 15*15mm^2. The number of I/O is less than 1500, mainly based on mobile phone communication and other related applications.
Figure 5: Today's flip-chips are still more mature than fan-out packages. Source: Yole (2017/09)
In the next five years, fan-out packages will gradually move toward multi-die System-in-Package, while fan-out packages are also oriented toward high-density (High I/O Density) - thin line width Developed and evolved toward larger fan-out multi-chip system-level packages, but packages with a package area greater than 40*40 mm^2 will still be dominated by flip-chip packages, while flip-chip packages will also be thinner. Line width and line spacing development.
Figure 6 The fan-out package will move toward a multi-wafer SiP package in the next five years. Source: Yole (2017/09)
After the next decade, multi-chip system-level fan-out package SiP has gradually become competitive with flip chip packaging technology, while the line width/line spacing<10/10 um carrier board has gradually matured, and FOSiP has gradually matured. The competition between flip chip packages and fan-out packages will increase, and the market for single- or multi-chip flip-chip packages (FCCSP-Single die/FCBGA-Multi die) will be seriously eroded in the trend of high-density fan-out packages becoming mature. Share, while the cost and performance of the two technologies are close together, the package form factor, industry chain and customer relationship will be the key to determine which package to use.
Figure 7 The SiP in a fan-out package for the next decade has competed with flip-chip packages. Source: Yole (2017/09)
Fourth, the industry development trend
Driven by the demand for electronic terminal products, the trend of wafer homogeneity/heterogeneity integration has become a market consensus, and the integration degree has been upgraded from PCB and carrier board to high-level wafer integration methods such as thin film process or 2.5D interposer. That is, the upcoming competition between the carrier and the test and test factory and even the fab, but the carrier has always been an important partner of the packaging and testing plant, so even if the customer is interested in high integration packaging, but Will the packaging and testing plant that has prepared the flip-chip packaging capacity be willing to abandon the long-established flip-chip packaging technology, and then invest in a large number of thin film processes to develop fan-out packaging technology? Or is it the development of high-density carrier boards in conjunction with the carrier plant with the existing chipping capacity? It is obvious that the latter is more likely, because the reinvestment cost of the former is mainly based on the packaging and testing plant, but the production capacity of the chipping may be vacant, so it may not be beneficial to the profit of the packaging and testing plant, and the investment cost of the latter is the carrier plant. Mainly, and in order to gain a competitive advantage, the carrier board is bound to continue to develop towards high-density carrier boards. Therefore, unless the package-free packaging technology and the capacity-packing test factory are more likely to actively develop fan-out type sealing and testing technology. The packaging and testing plant with the overlaying capacity has a relatively low willingness to reinvest in the fan-out package.